MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 467

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

16.3.2
The following paragraphs describe, in address order, all the VREG3V3V2 registers and their individual
bits.
16.3.2.1
The VREGCTRL register allows to separately enable features of VREG3V3V2.
16.4
Block VREG3V3V2 is a voltage regulator as depicted in
are the regulator core (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a
low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the
interface to the digital core logic but also manages the operating modes of VREG3V3V2.
Freescale Semiconductor
Module Base + 0x0000
Reset
LVDS
Field
LVIE
LVIF
2
1
0
W
R
Functional Description
Register Descriptions
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
VREG3V3V2 — Control Register (VREGCTRL)
0
0
7
On entering the Reduced Power Mode the LVIF is not cleared by the
VREG3V3V2.
= Unimplemented or Reserved
Figure 16-2. VREG3V3 — Control Register (VREGCTRL)
0
0
6
DDA
DDA
is above level V
is below level V
Table 16-3. MCCTL1 Field Descriptions
MC9S12C-Family / MC9S12GC-Family
0
0
5
LVIA
LVID
Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description
and FPM.
or RPM or shutdown mode.
Rev 01.24
NOTE
0
0
4
Description
Figure
0
0
3
16-1. The regulator functional elements
LVDS
0
2
LVIE
0
1
LVIF
0
0
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