MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 297

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

10.3.2.3
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Module Base + 0x0002
SJW[1:0]
BRP[5:0]
Field
7:6
5:0
Reset:
W
R
BRP5
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see
MSCAN Bus Timing Register 0 (CANBTR0)
0
0
0
0
1
:
SJW1
Table
0
7
SJW1
BRP4
10-5).
0
0
1
1
0
0
0
0
1
:
Table
Figure 10-6. MSCAN Bus Timing Register 0 (CANBTR0)
Table 10-4. Synchronization Jump Width
SJW0
Table 10-3. CANBTR0 Register Field Descriptions
BRP3
6
0
10-4).
0
0
0
0
1
:
Table 10-5. Baud Rate Prescaler
MC9S12C-Family / MC9S12GC-Family
BRP2
BRP5
0
0
0
0
1
:
0
5
SJW0
BRP1
0
1
0
1
0
0
1
1
1
:
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Rev 01.24
BRP4
4
0
BRP0
Description
0
1
0
1
1
:
BRP3
Synchronization Jump Width
0
3
Prescaler value (P)
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
BRP2
64
2
0
1
2
3
4
:
BRP1
0
1
BRP0
0
0
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