MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 452

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 15 Timer Module (TIM16B8CV1) Block Description
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
15.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN of TSCR1 is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
452
Module Base + 0x000F
C[7:0]F
Reset
Field
Field
TOF
7:0
7
W
R
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit when TEN is set to one.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
TOF
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit
requires writing a one to bit 7 of TFLG2 register while TEN bit of TSCR1 is set to one. (See also TCRE control
bit explanation.)
0
7
Unimplemented or Reserved
0
0
6
Figure 15-21. Main Timer Interrupt Flag 2 (TFLG2)
Table 15-17. TRLG1 Field Descriptions
Table 15-18. TRLG2 Field Descriptions
MC9S12C-Family / MC9S12GC-Family
0
0
5
Rev 01.24
0
0
4
Description
Description
0
0
3
0
0
2
Freescale Semiconductor
0
0
1
0
0
0