MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 205

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

7.3.2.7
1. When BKABEN is set (BKP mode), all bits in DBGC2 are available. When BKABEN is cleared and DBG is used in DBG mode,
2. These bits can be used in BKP mode and DBG mode (when capture mode is not set in LOOP1) to provide a third breakpoint.
Freescale Semiconductor
Module Base + 0x0028
Starting address location affected by INITRG register setting.
bits FULL and TAGAB have no meaning.
BKABEN
Reset
Field
Field
FULL
BDM
15:0
7
6
5
W
R
PAGSEL
BKABEN
x0
x1
Comparator C Compare Bits — The comparator C compare bits control whether comparator C will compare
the address bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode.
Breakpoint Using Comparator A and B Enable — This bit enables the breakpoint capability using comparator
A and B, when set (BKP mode) the DBGEN bit in DBGC1 cannot be set.
0 Breakpoint module off
1 Breakpoint module on
Full Breakpoint Mode Enable — This bit controls whether the breakpoint module is in dual mode or full mode.
In full mode, comparator A is used to match address and comparator B is used to match data. See
Section 7.4.1.2, “Full Breakpoint
0 Dual address mode enabled
1 Full breakpoint mode enabled
Background Debug Mode Enable — This bit determines if the breakpoint causes the system to enter
background debug mode (BDM) or initiate a software interrupt (SWI).
0 Go to software interrupt on a break request
1 Go to BDM on a break request
Debug Control Register 2 (DBGC2)
0
7
(1)
FULL
0
6
Figure 7-13. Debug Control Register 2 (DBGC2)
Table 7-12. DBGCC Field Descriptions
Table 7-14. DBGC2 Field Descriptions
Table 7-13. Comparator C Compares
EXTCMP[5:0] = XAB[21:16]
MC9S12C-Family / MC9S12GC-Family
BDM
EXTCMP Compare
0
5
Mode,” for more details.
No compare
TAGAB
Rev 01.24
0
4
Description
Description
Table
BKCEN
7-13.
0
3
Chapter 7 Debug Module (DBGV1) Block Description
(2)
DBGCCH[7:0] = XAB[15:14],AB[13:8]
TAGC
0
2
DBGCCH[7:0] = AB[15:8]
High-Byte Compare
2
RWCEN
0
1
2
RWC
0
0
2
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