CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 99

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

17.0
Table 17-1 and Table 17-2 show the AC timing parameters for the CYNSE70256 device. Table 17-3 shows the AC test conditions
for the CYNSE70256 device. Figure 17-1 shows the input wave form for the CYNSE70256 device. Figure 17-2 and Figure 17-3
show the output load and output load equivalent of the CYNSE70256 device. Figure 17-4 shows timing wave form diagrams for
CLK2X. Figure 17-5 details timing wave form diagrams for CLK1X.
Table 17-1. AC Timing Parameters with CLK2X
Table 17-2. AC Timing Parameters with CLK1X
Document #: 38-02035 Rev. *E
Notes:
43. Values are based on 50% signal levels.
44. Based on an AC load of C
45. These parameters are sampled but not 100% tested, and are based on an AC load of 5 pF.
46. Values are based on 50% signal levels and a 50%/50% duty cycle of CLK1X.
47. Based on an AC load of C
48. These parameters are sampled but not 100% tested, and are based on an AC load of 5 pF.
Parameter
Parameter
t
t
t
f
t
t
t
CKHSHZ
CKHSLZ
t
t
CLOCK
t
t
CKHOV
CKHDV
CKHDZ
CKHSV
t
t
t
ICSCH
ICHCH
t
t
f
t
t
t
t
CKHSHZ
CLOK
CKLO
CKHSLZ
IHCH
t
t
CKHI
ISCH
CLOCK
CKHOV
CKHDV
CKHDZ
CKHSV
t
t
t
ICHCH
t
t
ICSCH
CLOK
CKLO
CKHI
ISCH
IHCH
AC Timing Waveforms
CLK1X frequency.
PLL lock time.
CLK1X HIGH pulse; worst-case duty cycle.
CLK1X LOW pulse; worst-case duty cycle.
Input setup time to CLK1X edge.
Input hold time to CLK1X edge.
Cascaded input setup time to CLK1X rising edge.
Cascaded input hold time to CLK1X rising edge.
Rising edge of CLK1X to LHO, FULO, BHO, FULL valid.
Rising edge of CLK1X to DQ valid.
Rising edge of CLK1X to DQ HIGH-Z.
Rising edge of CLK1X to SRAM bus valid.
Rising edge of CLK1X to SRAM bus HIGH-Z.
Rising edge of CLK1X to SRAM bus LOW-Z.
CLK2X frequency.
PLL lock time.
CLK2X HIGH pulse.
CLK2X LOW pulse.
Input setup time to CLK2X rising edge.
Input hold time to CLK2X rising edge.
C]ascaded input setup time to CLK2X rising edge.
Cascaded input hold time to CLK2X rising edge.
Rising edge of CLK2X to LHO, FULO, BHO, FULL valid.
Rising edge of CLK2X to DQ valid.
Rising edge of CLK2X to DQ HIGH-Z.
Rising edge of CLK2X to SRAM bus valid.
Rising edge of CLK2X to SRAM bus HIGH-Z.
Rising edge of CLK2X to SRAM bus LOW-Z.
L
L
= 30 pF (see Figure 17-1, Figure 17-2, and Figure 17-3).
= 30 pF (see Figure 17-1, Figure 17-2, and Figure 17-3).
[43]
[43]
Description
Description
[46]
[46]
[47]
[44]
[48]
[43]
[45]
[43]
[47]
[46]
[46]
[48]
[44]
[48]
[45]
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[46]
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[43]
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CYNSE70256-066
CYNSE70256-066 CYNSE70256-083
Min.
3.0
3.0
2.5
0.6
4.2
2.0
0.5
0.5
7.0
6.75
6.75
40
Min
2.5
0.6
4.2
2.0
0.5
0.5
7.0
20
Max.
133
Max
0.5
8.5
9.0
8.5
9.0
6.5
0.5
8.5
9.0
8.5
9.0
6.5
66
CYNSE70256-083
Min.
Min
5.4
5.4
1.8
0.6
3.5
2.0
0.5
0.5
6.5
2.4
2.4
1.8
0.6
3.5
2.0
0.5
0.5
6.5
20
40
CYNSE70256
Max
Max.
0.5
7.0
7.5
7.0
7.5
6.0
166
83
0.5
7.0
7.5
7.0
7.5
6.0
Page 99 of 109
Unit
MHz
MHz
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns