CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 21

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The single Read operation takes six CLK cycles that operate in the following sequence.
At the termination of cycle 6, the selected device releases the ACK line to a three-state condition. The Read instruction is
complete, and a new operation can begin.
Table 10-5 describes the Read address format for the internal registers. Figure 10-2 illustrates the timing diagram for the burst
Read of the data or mask array.
Table 10-4. Read Address Format for Data Array, Mask Array, or SRAM
Document #: 38-02035 Rev. *E
Notes:
Reserved 0: Direct
Reserved 0: Direct
Reserved 0: Direct
12. “|” stands for logical OR operation. “{}” stands for concatenation operator.
11. The latency of the SRAM Read will be different than the one described above (see Subsection 12.1, “SRAM PIO Access,” on page 86). Table 10-4 lists and
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the DQ bus supplies
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives the ACK signal from Z to LOW.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[71:0] bus, and drives the ACK
• Cycle 6: The selected device floats the DQ[71:0] to a three-state condition and drives the ACK signal LOW.
[71:30]
the address, as shown in Table 10-4 and Table 10-5. The host ASIC selects the CYNSE70256 device for which ID[4:1] matches
the DQ[25:22] lines. The DQ[21] specifies the bank of the device. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70256
with the LDEV bit set. The host ASIC also supplies SADR[23:21] on CMD[8:6] in cycle A of the Read instruction if the Read
is directed to the external SRAM.
signal HIGH.
DQ
describes the format of the Read address for a data array, mask array, or SRAM.
1: Indirect
1: Indirect
1: Indirect
[29]
DQ
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
DQ[29] is indirect)
DQ[29] is indirect)
DQ[29] is indirect)
ACK
DQ
(applicable if
(applicable if
(applicable if
SSR Index
SSR Index
SSR Index
[28:26]
DQ
Figure 10-1. Single-Location Read Cycle Timing
[11]
[25:22]
DQ
cycle
ID
ID
ID
A
1
Address
Read
0 or 1
0 or 1
0 or 1
Bank
Bank
Bank
B
[21]
DQ
cycle
2
01: Mask
00: Data
External
[20:19]
SRAM
Array
Array
DQ
10:
cycle
3
Reserved If DQ[29] is 0, this field carries the address of
Reserved If DQ[29] is 0, this field carries the address of
Reserved If DQ[29] is 0, this field carries the address of
[18:16]
DQ
cycle
4
X
the data array location. If DQ[29] is 1, the SSR
index specified on DQ[28:26] is used to
generate the address of the data array
location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.
the mask array location. If DQ[29] is 1, the
SSR index specified on DQ[28:26] is used to
generate the address of the mask array
location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.
the SRAM location. If DQ[29] is 1, the SSR
index specified on DQ[28:26] is used to
generate the address of the SRAM location:
{SSR[15:2], SSR[1] | DQ[1], SSR[0] |
DQ[0]}.
cycle
5
[12]
[12]
[12]
Data
cycle
6
[15:0]
DQ
CYNSE70256
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