CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 92

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.5
The following explains the SRAM Write operation accomplished through a table of up to fifteen devices with the following
parameter: TLSZ = 10. The hardware diagram is shown in Figure 12-10. The following assumes that SRAM access is accom-
plished through the selected device: CYNSE70256 device number 0. Figure 12-11 and Figure 12-12 show timing diagrams for
device number 0 and device number 14, respectively.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM
bus with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
Document #: 38-02035 Rev. *E
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70256 device.
• Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70256 device.
DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle.
address with DQ[20:19] set to 10 to select the SRAM address.
SRAM Write with Table(s) Consisting of up to Fifteen Devices
SADR[23:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
Figure 12-9. SRAM Write Timing for Device Number 3 in Block of Four Devices
ACK
SSV
SSF
TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1
DQ
0
0
0
1
z
1
1
Address
cycle
Write
1
A B
01
cycle
2
x
cycle
3
x
cycle
4
[34]
cycle
5
cycle
6
1
[34]
cycle
7
z
z
z
z
cycle
8
0
1
1
1
cycle
9
cycle
10
CYNSE70256
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