CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 86

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.0
Table 12-1 describes the commands used to generate addresses on the SRAM address bus. The index [15:0] field contains the
address of a 72-bit entry that results in a hit in 72-bit-configured quadrant. It is the address of the 72-bit entry that lies at the 144-
bit page, and the 288-bit page boundaries in 144-bit- and 288-bit-configured quadrants, respectively.
Section 7.0, “Registers,” on page 13 of this datasheet describes the NFA and SSR registers. ADR[15:0] contains the address
supplied on the DQ bus during PIO access to the CYNSE70256. Command bits 8, 7, and 6 {CMD[8:6]} are passed from the
command to the SRAM address bus. See Section 10.0, “Commands,” on page 19, for more information. ID[4:0] is the ID of the
device driving the SRAM bus (see Section 18.0, “Pinout Descriptions and Package Diagrams,” on page 103, for more infor-
mation).
Table 12-1. SRAM Bus Address
12.1
The remainder of Section 12.0 describes SRAM Read and Write operations.
SRAM Read enables Read access to the off-chip SRAM containing associative data. The latency from the issuance of the Read
instruction to the appearance of the address on the SRAM bus is the same as the Search instruction latency, and will depend on
the value programmed for the TLSZ parameter in the device configuration register. The latency of the ACK from the Read
instruction is the same as that from the Search instruction to the SRAM address latency, plus the HLAT programmed in the
configuration register.
Notes:
Document #: 38-02035 Rev. *E
32. SRAM Read is a blocking operation—no new instruction can begin until the ACK is returned by the selected device performing the access. SRAM Write enables
33. SRAM Write is a pipelined operation.
Indirect Access
Write access to the off-chip SRAM containing associative data. The latency from the second cycle of the Write instruction to the appearance of the address on
the SRAM bus is the same as the Search instruction latency, and will depend on the TLSZ value parameter programmed in the device configuration register.
Command
PIO Read
PIO Write
Search
Learn
CMDV
CMD[10:0]
SSF, SSV
DQ[71:0]
SRAM PIO Access
SRAM Addressing
[32, 33]
SRAM Operation
Write/Read
Read
Write
Read
Write
Figure 11-3. FULL Signal Generation in a Cascaded Table
C8
C8
C8
C8
C8
23
CYNSE70256 #0
CYNSE70256 #1
CYNSE70256 #2
CYNSE70256 #3
C7
C7
C7
C7
C7
22
0
FULO[1]
C6
C6
0
0
0
C6
C6
C6
21
FULO[1]
1
1
1
1
FULO[1]
2
2
2
2
[20:17]
ID[4:1]
ID[4:1]
ID[4:1]
ID[4:1]
ID[4:1]
FULI
LHI
LHI
FULO[1]
FULO[0]
3
3
3
3
FULI
FULO[0]
4
4
4
FULO[0]
4
5
5
5
bank
bank
bank
bank
bank
5
16
FULO[0]
6
6
6
6
V
V
CYNSE70256
V
V
DD
DD
FULL
DD
DD
Index[15:0]
ADR[15:0]
SSR[15:0]
NFA[15:0]
ADR16:0]
[15:0]
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SRAM