XRP7714ILB-0X18-F Exar Corporation, XRP7714ILB-0X18-F Datasheet - Page 6

• Manufacturer Part Number: XRP7714ILB-0X18-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Series: -r

Specifications of XRP7714ILB-0X18-F

• Topology: Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 5
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 4.75 V ~ 25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1699

PIN ASSIGNMENT
PIN DESCRIPTION
© 2011 Exar Corporation
PGND14
Name
DVDD
AGND
VCCD
AVDD
VCCA
DGND
VIN1
VIN2
Pin Number
36,31,16,21 Power Ground. Ground connection for the low side gate driver. Connect at low side FET source.
GPIO4_SDA
GPIO5_SCL
39
38
37
26
10
11
1
2
ENABLE
GPIO0
GPIO1
GPIO2
GPIO3
DGND
AVDD
DVDD
Power source for the internal linear regulators to generate VCCA, VDD and the Standby LDO
(LDOOUT). Place a decoupling capacitor close to the controller IC. Also used in UVLO1 fault
generation – if VIN1 falls below the user programmed limit, all channels are shut down. The
VIN1 pin needs to be tied to VIN2 on the board with a short trace.
If the VIN2 pin voltage falls below the user programmed UVLO VIN2 level all channels are shut
down. The VIN2 pin needs to be tied to VIN1 on the board with a short trace.
Output of the internal 5V LDO. This voltage is internally used to power analog blocks. This pin
should be bypassed with a minimum of 4.7uF to AGND
Gate Drive input voltage. This is not an output voltage. This pin can be connected to VCCA to
provide power for the Gate Drive. VCCD should be connected to VCCA with the shortest
possible trace and decouple with a minimum 1µF capacitor. Alternatively, VCCD could be
connected to an external supply (not greater than 5V).
Output of the internal 1.8V LDO. This pin should be bypassed with a minimum of 2.2uF to
DGND
Input for powering the internal digital logic. This pin should be connected to AVDD.
Digital Ground. Connect this pin to the ground plane at the exposed pad with a separate trace.
Analog Ground. Connect this pin to the ground plane at the exposed pad with a separate trace
10
1
2
3
4
5
6
7
8
9
Q
Q
u
u
Fig. 3: XRP7714 Pin Assignment
a
a
d
d
C
C
h
h
Exposed Pad: AGND
6mm X 6mm
a
a
XRP7714
n
n
6/29
TQFN
n
n
e
e
l
l
D
D
Description
i
i
g
g
i
i
t
t
a
a
l
l
P
P
W
W
M
M
S
S
t
t
e
e
30
29
28
27
26
25
24
23
22
21
p
p
D
D
GL2
LX2
GH2
BST2
VCCD
BST4
GH4
LX4
GL4
PGND4
o
o
w
w
n
n
X
X
C
C
R
R
o
o
n
P
n
P
Rev. 1.1.6
t
t
7
7
r
r
o
o
7
7
l
l
1
1
l
l
e
e
4
4
r
r