XRP7714ILB-0X18-F Exar Corporation, XRP7714ILB-0X18-F Datasheet - Page 22

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XRP7714ILB-0X18-F

Manufacturer Part Number
XRP7714ILB-0X18-F
Description
IC CTRLR PWM/LDO STP-DWN 40TQFN
Manufacturer
Exar Corporation
Series
-r
Datasheet

Specifications of XRP7714ILB-0X18-F

Topology
Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
Function
Any Function
Number Of Outputs
5
Frequency - Switching
1.5MHz
Voltage/current - Output 1
Controller
Voltage/current - Output 2
Controller
Voltage/current - Output 3
Controller
W/led Driver
No
W/supervisor
No
W/sequencer
Yes
Voltage - Supply
4.75 V ~ 25 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1016-1699
Two XRP7714s can be synchronized together. This Master-Slave configuration is described below.
When the XRP7714 powers up as a master unit after the internal configuration memory is loaded
the unit will send CLK_OUT and SYNC_OUT signals to the slave on the preconfigured GPIO pins.
When powering in sync mode the slave unit will initially power up with its internal clock to transfer
the configuration memory. Once this transfer occurs, then the unit is set to function as a slave unit.
In turn the unit will take the external clock provided by the master to run as its main internal clock.
When an external clock is used, the user will need to setup the master to also have an external
clock in function. All of the same rules apply as in the External clock synchronization, Synchronized
operation as a Slave unit section of this document.
either the external clock going to both Master/Slave CLK_IN, or CLK_IN can go to the Master, and
the Master can synchronize SYNC_OUT and CLK_OUT to the Slave.
© 2011 Exar Corporation
Synchronized Operation as a Master and Slave Unit
External Clock Synchronization Master Slave combination
Master
Slave
CLK_IN
Fig. 29: External Clock Synchronization Master Slave Combination
as a master
Fig. 28: Master/Slave Configuration of the XRP7714
configured
XRP7714
external clock sync
GPIO1
Configured as a
GPIO1
GPIO2
master with
Q
Q
XRP7714
u
u
a
a
CLK_OUT
SYNC_OUT
d
d
GPIO2
C
C
h
h
a
SYNC_OUT
a
22/29
n
n
n
n
e
e
l
l
SYNC_IN
CLK_IN
D
D
There are two ways of synchronizing this,
i
i
g
g
i
i
SYNC_IN
t
t
CLK_IN
a
a
GPIO2
GPIO1
l
l
configured
as a slave
P
XRP7714
P
W
W
GPIO2
GPIO1
M
M
configured
XRP7714
as slave
S
S
t
t
e
e
p
p
D
D
o
o
w
w
n
n
X
X
C
C
R
R
o
o
n
P
n
P
Rev. 1.1.6
t
t
7
7
r
r
o
o
7
7
l
l
1
1
l
l
e
e
4
4
r
r

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