SC16IS850LIPW,128 NXP Semiconductors, SC16IS850LIPW,128 Datasheet - Page 6

• Manufacturer Part Number: SC16IS850LIPW,128
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIPW,128

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16IS850L
Product data sheet
Table 2.
[1]
Symbol
RTS
DSR
CD
RI
DTR
n.c.
HVQFN24 package die supply ground is connected to both V
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
printed-circuit board in the thermal pad region.
Pin description
Pin
HVQFN24
16
19
20
21
11
6, 10,
12, 23
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2011
TSSOP24
13
17
18
19
8
3, 7, 9, 14
…continued
-
Type
O
I
I
I
O
Description
UART request to send (active LOW).
A logic 0 on the RTS pin indicates the transmitter
has data ready and waiting to send. Writing a
logic 1 in the Modem Control Register MCR[1]
will set this pin to a logic 0, indicating data is
available. After reset, this pin is set to a logic 1.
This pin only affect the transmit and receive
operations when Auto-RTS function is enabled
via the Enhanced Feature Register (EFR[6]) for
hardware flow control operation.
Data set ready. DSR is a modem status signal.
Its condition can be checked by reading MSR[5].
MSR[1] indicates DSR has changed levels since
the last read from the modem status register. If
the modem status interrupt is enabled when DSR
changes levels, an interrupt is generated.
Data carrier detect. CD is a modem status signal.
Its condition can be checked by MSR[7]. MSR[3]
indicates that CD has changed states since the
last read from the modem status register. If the
modem status interrupt is enabled when CD
changes levels, an interrupt is generated.
Ring indicator. RI is a modem status signal. Its
condition can be checked by reading MSR[6].
MSR[2] indicates that RI has transitioned from a
LOW to a HIGH level since the last read from the
modem status register. If the modem status
interrupt is enabled when this transition occurs,
an interrupt is generated.
Data terminal ready. When active (LOW), DTR
informs a modem or data set that the UART is
ready to establish communication. DTR is placed
in the active level by setting the DTR bit of the
modem control register. DTR is placed in the
inactive level either as a result of a Master
Reset, during Loopback mode operation, or
clearing the DTR bit.
Not connected; these pins should be left open.
Single UART with I
SS
pin and exposed center pad. V
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
SS
pin must
6 of 60