SC16IS850LIPW,128 NXP Semiconductors, SC16IS850LIPW,128 Datasheet - Page 25

• Manufacturer Part Number: SC16IS850LIPW,128
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIPW,128

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16IS850L
Product data sheet
8.5 Line Control Register (LCR)
Table 12.
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 13.
Table 14.
Table 15.
Bit
0
Bit
7
6
5:3
1:0
LCR[5]
LCR[2]
0
1
1
2
X
0
0
1
1
Symbol
ISR[0]
Symbol
LCR[7]
LCR[6]
LCR[5:3]
LCR[2]
LCR[1:0]
Interrupt Status Register bits description
Line Control Register bits description
LCR[5:3] parity selection
LCR[2] stop bit length
LCR[4]
X
0
1
0
1
Word length (bits)
5, 6, 7, 8
5
6, 7, 8
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INT status.
Divisor latch enable. The internal baud rate counter latch and Enhanced
Set break. When enabled, the Break control bit causes a break condition to
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in conjunction with the
Word length bits 1, 0. These two bits specify the word length to be
Description
Description
Feature mode enable.
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
programmed word length (see
transmitted or received (see
LCR[3]
0
1
1
1
1
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Rev. 1 — 22 July 2011
Stop bit length (bit times)
1
1
2
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
1
⁄
2
Table
Single UART with I
Table
…continued
16).
Table
15).
14).
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
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