SC16IS850LIPW,128 NXP Semiconductors, SC16IS850LIPW,128 Datasheet - Page 32

• Manufacturer Part Number: SC16IS850LIPW,128
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIPW,128

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16IS850L
Product data sheet
8.17 Flow Control Trigger Level High (FLWCNTH)
8.18 Flow Control Trigger Level Low (FLWCNTL)
8.19 Clock Prescaler (CLKPRES)
[1]
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 25.
[1]
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control.
register bit settings; see
Table 26.
[1]
This register hold values for the clock prescaler.
Table 27.
Bit
7:0
Bit
7:0
Bit
7:4
3:0
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
FLWCNTH[7:0]
FLWCNTL[7:0]
Symbol
Symbol
Symbol
CLKPRES[7:4]
CLKPRES[3:0]
FLWCNTH register bits description
FLWCNTL register bits description
Clock Prescaler register bits description
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2011
Section
Section
This register stores the programmable HIGH threshold level for
This register stores the programmable LOW threshold level for
reserved
Clock Prescaler value. Reset to 0.
Description
hardware and software flow control for 128-byte FIFO mode
Description
hardware and software flow control for 128-byte FIFO mode
Description
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Section
Section
Section
7.4.
7.4.
8.3.
8.3.
8.3.
Single UART with I
Table 25
Table 26
shows the FLWCNTH
shows the FLWCNTL
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
[1]
[1]
32 of 60
.
.