SC16IS850LIPW,128 NXP Semiconductors, SC16IS850LIPW,128 Datasheet - Page 10

• Manufacturer Part Number: SC16IS850LIPW,128
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIPW,128

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16IS850L
Product data sheet
7.5 Software flow control
With the automatic hardware flow control function enabled, an interrupt is generated when
the receive FIFO reaches the programmed trigger level. The RTS (or DTR) pin will not be
forced to a logic 1 (RTS off), until the receive FIFO reaches the next trigger level.
However, the RTS (or DTR) pin will return to a logic 0 after the receive buffer (FIFO) is
unloaded to the next trigger level below the programmed trigger level. Under the above
described conditions, the SC16IS850L will continue to accept data until the receive FIFO
is full.
When the TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL in the ‘first extra feature
register set’ are all zeroes, the hardware and software flow control trigger levels are set by
FCR[7:4]; see
When the TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature
register set’ contain any value other than 0x00, the hardware and software flow control
trigger levels are set by FLWCNTH and FLWCNTL. The content in FLWCNTH determines
how many bytes are in the receive FIFO before RTS (or DTR) is de-asserted or Xoff is
sent. The content in FLWCNTL determines how many bytes are in the receive FIFO
before RTS (or DTR) is asserted, or Xon is sent.
In 128-byte FIFO mode, hardware and software flow control trigger levels can be set to
any value between 1 and 128 in granularity of 1. The value of FLWCNTH should always
be greater than FLWCNTL. The UART does not check for this condition automatically, and
if this condition is not met, spurious operation of the device might occur. When using
FLWCNTH and FLWCNTL, these registers must be initialized to proper values before
hardware or software flow control is enabled via the EFR register.
When software flow control is enabled, the SC16IS850L compares one or two
sequentially received data characters with the programmed Xon or Xoff character
value(s). If the received character(s) match the programmed Xoff values, the SC16IS850L
will halt transmission (TX) as soon as the current character(s) has completed
transmission. When a match occurs, ISR bit 4 will be set (if enabled via IER[5]) and the
interrupt output pin (if receive interrupt is enabled) will be activated. Following a
suspension due to a match of the Xoff characters’ values, the SC16IS850L will monitor
the receive data stream for a match to the Xon1/Xon2 character value(s). If a match is
found, the SC16IS850L will resume operation and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions (see
SC16IS850L compares two consecutive receive characters with two software flow control
8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under
the above described flow control mechanisms, flow control characters are not placed
(stacked) in the receive FIFO. When using software flow control, the Xon/Xoff characters
cannot be used for data transfer.
In the event that the receive buffer is overfilling, the SC16IS850L automatically sends an
Xoff character (when enabled) via the serial TX output to the remote UART. The
SC16IS850L sends the Xoff1/Xoff2 characters as soon as the number of received data in
Table
All information provided in this document is subject to legal disclaimers.
Table
4.
Rev. 1 — 22 July 2011
22). When double 8-bit Xon/Xoff characters are selected, the
Single UART with I
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
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