SC16IS850LIPW,112 NXP Semiconductors, SC16IS850LIPW,112 Datasheet - Page 37

• Manufacturer Part Number: SC16IS850LIPW,112
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIPW,112

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16IS850L
Product data sheet
Fig 11. Data transfer on the I
Fig 12. Acknowledge on the I
SDA
SCL
condition
SCL from master
START
by transmitter
S
data output
data output
by receiver
9.2 Addressing and transfer formats
MSB
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.
There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when
a master is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
The second exception is that a slave will send a negative acknowledge when it can no
longer accept additional data bytes. This occurs after an attempted transfer that cannot be
accepted.
Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
first byte transmitted by the master after the START condition.
0
condition
START
2
S
1
2
C-bus
C-bus
interrupt within receiver
All information provided in this document is subject to legal disclaimers.
0
6
byte complete,
1
Rev. 1 — 22 July 2011
7
ACK
8
acknowledgement signal
from receiver
6
7
0
clock line held LOW
while interrupt is serviced
8
1
002aab013
Single UART with I
2 to 7
transmitter stays off of the bus
during the acknowledge clock
acknowledgement signal
from receiver
ACK
8
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
condition
STOP
P
002aab012
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