SC16IS850LIPW,112 NXP Semiconductors, SC16IS850LIPW,112 Datasheet - Page 16

• Manufacturer Part Number: SC16IS850LIPW,112
• Manufacturer: NXP Semiconductors

Specifications of SC16IS850LIPW,112

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SC16IS850L
Product data sheet
7.10.1 Conditions to enter Sleep mode
7.10.2 Conditions to resume normal operation
7.10 Sleep mode
Sleep mode is an enhanced feature of the SC16IS850L UART. It is enabled when EFR[4],
the enhanced functions bit, is set and when IER[4] bit is set.
Sleep mode is entered when:
In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are
clocked using these clocks, the power consumption is greatly reduced.
Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be
done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4]
before writing to DLL or DLM.
SC16IS850L resumes normal operation by any of the following:
If the device is awakened by one of the conditions described above, it will return to the
Sleep mode automatically after all the conditions described in
device will stay in Sleep mode until it is disabled by setting any channel’s IER bit 4 to a
logic 0.
Wake-up by serial data on RX input pin is supported in UART mode but not in IrDA mode.
Refer to application note AN19064, “How to wake up SC16IS740/750/760 in IrDA mode”
for a software procedure to wake up the device by receiving data in IrDA mode.
When the SC16IS850L is in Sleep mode and the host data bus (D[7:0], A[2:0], IOW, IOR,
CS) remains in steady state, either HIGH or LOW, the Sleep mode supply current will be
in the A range as specified in
toggling or floating then the sleep current will be higher.
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Modem input pins are not toggling.
The serial data input line, RX, is idle for 4 character time (logic HIGH) and AFCR1[4]
is logic 0. When AFCR1[4] is logic 1 the device will go to sleep regardless of the state
of the RX pin (see
The TX FIFO and TX shift register are empty.
There are no interrupts pending.
The RX FIFO is empty.
Receives a start bit on RX pin.
Data is loaded into transmit FIFO.
A change of state on any of the modem input pins
All information provided in this document is subject to legal disclaimers.
Section 8.21
Rev. 1 — 22 July 2011
Table 37 “Static
for the description of AFCR1 bit 4).
characteristics”. If any of these signals is
Single UART with I
Section 7.10.1
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
are met. The
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