MT16HTF25664HZ-667H1 Micron Technology Inc, MT16HTF25664HZ-667H1 Datasheet - Page 15

• Manufacturer Part Number: MT16HTF25664HZ-667H1
• Description: MODULE DDR2 SDRAM 2GB 200SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT16HTF25664HZ-667H1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 667MT/s
• Features: -
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 256Mx64
• Total Density: 2GByte
• Chip Density: 128Mb
• Access Time (max): 900ns
• Package Type: SODIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.136A
• Number Of Elements: 16
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 13: DDR2 I
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. C 9/10 EN
Parameter
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
(I
trol and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
=
are switching; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
=
valid commands; Address bus inputs are stable during deselects; Data bus inputs
are switching
CK =
OUT
OUT
DD
t
t
RP (I
RC (I
),
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
RP =
CK (I
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DD
t
t
RP (I
RRD =
); CKE is LOW; Other control and address
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
t
), AL = 0;
RRD (I
DD
Notes:
Specifications and Conditions – 4GB (Die Revision A) (Continued)
t
CK =
DD
),
t
DD
DD
CK =
t
t
RCD =
CK (I
1. Value calculated as one module rank in this operating condition; all other module ranks
2. Value calculated reflects all module ranks in this operating condition.
), AL = 0;
), AL =
in I
t
CK (I
DD
t
DD2P
); REFRESH command at every
RCD (I
t
RCD (I
DD
t
1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
CK =
),
(CKE LOW) mode.
t
DD
RAS =
DD
); CKE is HIGH, S# is HIGH between
t
CK (I
) - 1 ×
t
CK =
t
RAS MAX (I
DD
t
CK =
t
),
CK (I
t
t
CK (I
Fast PDN exit MR[12] = 0
Slow PDN exit MR[12] = 1
RAS =
t
DD
t
CK (I
CK =
15
DD
);
DD
t
t
),
DD
RAS MAX (I
CK =
t
),
t
CK (I
); CKE is HIGH,
RAS =
t
RP =
t
RFC (I
t
CK (I
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
); CKE is
t
RAS MAX
RP (I
DD
DD
DD
) inter-
),
),
DD
t
RC
t
RP
);
Symbol
I
I
I
I
I
I
DD4W
DD2Q
DD2N
DD3N
I
I
I
DD3P
DD4R
DD5
DD6
DD7
2
2
1
2
2
2
1
2
1
© 2008 Micron Technology, Inc. All rights reserved.
IDD Specifications
-1GA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-80E/
-800 -667 Units
1040
1120
1040
1536 1376
1616 1456
2496 2336
3216 2816
720
224
192
880
960
640
224
880
192
mA
mA
mA
mA
mA
mA
mA
mA
mA