MT16HTF25664HZ-667H1 Micron Technology Inc, MT16HTF25664HZ-667H1 Datasheet - Page 6

• Manufacturer Part Number: MT16HTF25664HZ-667H1
• Description: MODULE DDR2 SDRAM 2GB 200SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT16HTF25664HZ-667H1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 667MT/s
• Features: -
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 256Mx64
• Total Density: 2GByte
• Chip Density: 128Mb
• Access Time (max): 900ns
• Package Type: SODIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.136A
• Number Of Elements: 16
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Description
Serial Presence-Detect Operation
PDF: 09005aef8339ef97/Source: 09005aef8339eff3
HTF16C128_256x64HZ.fm - Rev. A 5/08 EN
The MT16HTF12864H and MT16HTF25664H are DDR2 SDRAM high-speed CMOS,
dynamic random-access 1GB and 2GB memory modules, organized in a x64 configura-
tion. These DDR2 SDRAM modules use internally configured, 4-bank (512Mb) or 8-bank
(1Gb) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Clock,
control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module
type and various SDRAM organizations and timing parameters. The remaining 128 bytes
of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I
which provide four unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
on the module, permanently disabling hardware write protect.
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[1:0],
1GB, 2GB (x64, DR) 200-Pin Halogen-Free DDR2 SDRAM SODIMM
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2008 Micron Technology, Inc. All rights reserved
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