PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 9

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIST OF TABLES
Table 2-1. Pin List – 208-pin FQFP............................................................................................................ 18
Table 2-2. Pin List – 256-pin PBGA............................................................................................................ 20
Table 3-1. PCI Transactions ........................................................................................................................ 22
Table 3-2. Write Transaction Forwarding .................................................................................................. 23
Table 3-3. Write Transaction Disconnect Address Boundaries................................................................... 26
Table 3-4. Read Prefetch Address Boundaries............................................................................................ 28
Table 3-5. Read Transaction Prefetching.................................................................................................... 28
Table 3-6. Device Number to IDSEL S_AD Pin Mapping........................................................................... 32
Table 3-7. Delayed Write Target Termination Response ............................................................................ 37
Table 3-8. Response to Posted Write Target Termination........................................................................... 37
Table 3-9. Response to Delayed Read Target Termination......................................................................... 38
Table 5-1. Summary of Transaction Ordering ............................................................................................ 48
Table 6-1. Setting the Primary Interface Detected Parity Error Bit ........................................................... 56
Table 6-2. Setting Secondary Interface Detected Parity Error Bit.............................................................. 57
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit ............................................ 57
Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit......................................... 58
Table 6-5. Assertion of P_PERR_L ............................................................................................................. 58
Table 6-6. Assertion of S_PERR_L.............................................................................................................. 59
Table 6-7. Assertion of P_SERR_L for Data Parity Errors......................................................................... 60
Table 10-1. GPIO Operation....................................................................................................................... 69
Table 10-2. GPIO Serial Data Format........................................................................................................ 70
Table 11-1. Power Management Transitions .............................................................................................. 71
Table 16-1. TAP Pins .................................................................................................................................. 99
Table 16-2. JTAG Boundary Register Order............................................................................................. 101
LIST OF FIGURES
Figure 8-1
Figure 16-1
Figure 17-1
Figure 18-1
Figure 18-2
Secondary Arbiter Example.................................................................................................... 65
Test Access Port Block Diagram .......................................................................................... 98
PCI Signal Timing Measurement Conditions ..................................................................... 105
208-pin FQFP Package Outline......................................................................................... 107
256-pin PBGA Package Outline......................................................................................... 108
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B