PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 24

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”
transactions.
When PI7C8150B determines that a memory write transaction is to be forwarded across the
bridge, PI7C8150B asserts DEVSEL_L with medium timing and TRDY_L in the next
cycle, provided that enough buffer space is available in the posted memory write queue for
the address and at least one DWORD of data. Under this condition, PI7C8150B accepts
write data without obtaining access to the target bus. The PI7C8150B can accept one
DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The
write data is stored in an internal posted write buffers and is subsequently delivered to the
target. The PI7C8150B continues to accept write data until one of the following events
occurs:
When one of the last two events occurs, the PI7C8150B returns a target disconnect to the
requesting initiator on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C8150B asserts
its request on the target bus. This can occur while PI7C8150B is still receiving data on the
initiator bus. When the grant for the target bus is received and the target bus is detected in
the idle condition, PI7C8150B asserts FRAME_L and drives the stored write address out
on the target bus. On the following cycle, PI7C8150B drives the first DWORD of write
data and continues to transfer write data until all write data corresponding to that
transaction is delivered, or until a target termination is received. As long as write data
exists in the queue, PI7C8150B can drive one DWORD of write data each PCI clock cycle;
that is, no master wait states are inserted. If write data is flowing through PI7C8150B and
the initiator stalls, PI7C8150B will signal the last data phase for the current transaction at
the target bus if the queue empties. PI7C8150B will restart the follow-on transactions if the
queue has new data.
PI7C8150B ends the transaction on the target bus when one of the following conditions is
met:
The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
An internal write address boundary is reached, such as a cache line boundary or an
aligned 4KB boundary, depending on the transaction type.
The posted write data buffer fills up.
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C8150B starts another
transaction to deliver the rest of the write data).
The target returns a target abort (PI7C8150B discards remaining write data).
The master latency timer expires, and PI7C8150B no longer has the target bus grant
(PI7C8150B starts another transaction to deliver remaining write data).
Page 24 of 109
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B