PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 54

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Similarly, for upstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150B has write status to return, the following events occur:
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
PI7C8150B sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C8150B first asserts S_TRDY_L and then asserts S_PERR_L two cycles later, if
the secondary interface parity-error-response bit is set in the bridge control register
(offset 3Ch).
PI7C8150B sets the secondary interface parity-error-detected bit in the secondary
status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the following are
both true:
PI7C8150B completes the transaction normally.
PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the following are
both true:
PI7C8150B completes the transaction normally.
The parity-error-response bit is set in the command register of the primary
interface.
The parity-error-response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the
secondary interface.
Page 54 of 109
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B