PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 78

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.4
STATUS REGISTER – OFFSET 04h
Bit
7
8
9
15:10
Bit
19:16
20
21
22
23
24
26:25
27
28
29
Function
Wait Cycle
Control
P_SERR_L
enable
Fast Back-to-
Back Enable
Reserved
Function
Reserved
Capabilities List
66MHz Capable
Reserved
Fast Back-to-
Back Capable
Data Parity Error
Detected
DEVSEL_L
timing
Signaled Target
Abort
Received Target
Abort
Received Master
Abort
Type
R/O
R/W
R/W
R/O
Type
R/O
R/O
R/O
R/O
R/O
R/WC
R/O
R/WC
R/WC
R/WC
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Description
Controls the ability to perform address / data stepping
0: disable address/data stepping (affects primary and secondary)
1: enable address/data stepping (affects primary and secondary)
Reset to 0
Controls the enable for the P_SERR_L pin
0: disable the P_SERR_L driver
1: enable the P_SERR_L driver
Reset to 0
Controls 7C8150’s ability to generate fast back-to-back transactions
to different devices on the primary interface.
0: no fast back-to-back transactions
1: enable fast back-to-back transactions
Reset to 0
Returns 000000 when read
Description
Reset to 0
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1
Set to 1 to enable 66MHz operation on the primary interface
Reset to 1
Reset to 0
Set to 1 to enable decoding of fast back-to-back transactions on the
primary interface to different targets
Reset to 1
Set to 1 when P_PERR_L is asserted and bit 6 of command register
is set
Reset to 0
DEVSEL_L timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
Set to 1 (by a master device) whenever transactions are terminated
with target aborts
Reset to 0
Set to 1 (by a master) when transactions are terminated with Master
Abort
Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B