PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 83

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.21
14.1.22
14.1.23
14.1.24
14.1.25
14.1.26
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
ECP POINTER REGISTER – OFFSET 34h
INTERRUPT LINE REGISTER – OFFSET 3Ch
Bit
31:0
Bit
31:0
Bit
15:0
Bit
31:0
Bit
7:0
Bit
7:0
Function
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
Function
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
Function
I/O Base
Address, Upper
16-bits [31:16]
Function
I/O Limit
Address, Upper
16-bits [31:16]
Function
Enhanced
Capabilities Port
Pointer
Function
Interrupt Line
Type
R/W
Type
R/W
Type
R/W
Type
R/W
Type
R/O
Type
R/W
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Description
Defines the upper 32-bits of a 64-bit bottom address of an address
range for the bridge to determine when to forward memory read and
write transactions from one interface to the other.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit top address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit bottom address of an address
range for the bridge to determine when to forward I/O transactions
from one interface to the other.
Reset to 0
Description
Defines the upper 16-bits of a 32-bit top address of an address range
for the bridge to determine when to forward I/O transactions from
one interface to the other.
Reset to 0
Description
Enhanced capabilities port offset pointer. Read as DCh to indicate
that the first item resides at that configuration offset.
Description
For POST to program to FFh, indicating that the PI7C8150B does not
implement an interrupt pin.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B