PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 71

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11
Table 11-1. Power Management Transitions
To enable live insertion mode, the live insertion mode bit in the chip control register must
be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO
output enable control register. When live insertion mode is enabled, whenever GPIO[3] is
driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are
internally masked to 0. This means that, as a target, PI7C8150B no longer accepts any I/O
or memory transactions, on either interface. When read, the register bits still reflect the
value originally written by a configuration write command; when GPIO[3] is deasserted,
the internal enable bits return to their original value (as they appear when read from the
command register). When this mode is enabled, as a master, PI7C8150B completes any
posted write or delayed request transactions that have already been queued.
Delayed completion transactions are not returned to the master in this mode because
PI7C8150B is not responding to any I/O or memory transactions during this time.
PI7C8150B continues to accept configuration transactions in live insertion mode. Once live
insertion mode brings PI7C8150B to a halt and queued transactions are completed, the
secondary reset bit in the bridge control register can be used to assert S_RST_L, if desired,
to reset and tri-state secondary bus devices, and to enable any live insertion hardware.
PCI POWER MANAGEMENT
PI7C8150B incorporates functionality that meets the requirements of the PCI Power
Management Specification, Revision 1.0. These features include:
Table 11-1 shows the states and related actions that PI7C8150B performs during power
management transitions. (No other transactions are permitted.)
D0
D0
D0
D0
D3hot
D3hot
Current Status
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
Support for D0, D3
Support for D0, D1, D2, D3
behind the bridge
Support of the B2 secondary bus power state when in the D3
state
D3cold
D3hot
D2
D1
D0
D3cold
Next State
hot
and D3
Page 71 of 109
hot
cold
Power has been removed from PI7C8150B. A power-up reset must
be performed to bring PI7C8150B to D0.
If enabled to do so by the BPCCE pin, PI7C8150B will disable the
secondary clocks and drive them LOW.
Unimplemented power state. PI7C8150B will ignore the write to the
power state bits (power state remains at D0).
Unimplemented power state. PI7C8150B will ignore the write to the
power state bits (power state remains at D0).
PI7C8150B enables secondary clock outputs and performs an internal
chip reset. Signal S_RST_L will not be asserted. All registers will
be returned to the reset values and buffers will be cleared.
Power has been removed from PI7C8150B. A power-up reset must
be performed to bring PI7C8150B to D0.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
, and D3
power management states
cold
power management states for devices
ADVANCE INFORMATION
Action
April 2009 – Revision 1.08
hot
power management
PI7C8150B