PCA9574HR,115 NXP Semiconductors, PCA9574HR,115 Datasheet - Page 9

• Manufacturer Part Number: PCA9574HR,115
• Description: IC I/O EXPANDER I2C 8B 16HXQFN
• Manufacturer: NXP Semiconductors

Specifications of PCA9574HR,115

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-XQFN (Exposed Pad), 16-eXQFN, 16-HXQFN
• Includes: POR
• Logic Family: CMOS
• Number Of Lines (input / Output): 8 / 8
• Operating Supply Voltage: 1.1 V to 3.6 V
• Power Dissipation: 75 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 1.1 V to 4.1 V
• Logic Type: I2C Bus Extender
• Maximum Clock Frequency: 400 KHz
• Maximum Operating Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8
• Number Of Output Lines: 8
• Output Current: +/- 5 mA
• Output Voltage: 1.1 V to 4.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4936-2

NXP Semiconductors
PCA9574_2
Product data sheet
7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register
Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank. In this mode, the
pull-up/pull-downs will be disabled. Setting the bit 0 to logic 0 disables bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 3. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O pins and contents of Register 3
will have no effect on the I/O.
Table 7.
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Symbol
E0.7
E0.6
E0.5
E0.4
E0.3
E0.2
E0.1
E0.0
Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit
description
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 02 — 27 July 2009
8-bit I
Value
X
X
X
X
X
X
0*
0*
2
C-bus and SMBus, level translating, low voltage GPIO
Description
not used
allows the user to enable/disable pull-up/pull-downs on the
I/O pins
allows user to enable/disable the bus-hold feature for the I/O
pins
0 = disables pull-up/pull-downs on the I/O pins and
contents of Register 3 will have no effect on the I/O
(default value)
1 = enables selection of pull-up/pull-down using
Register 3
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature
PCA9574
© NXP B.V. 2009. All rights reserved.
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