PCA9574HR,115 NXP Semiconductors, PCA9574HR,115 Datasheet - Page 15

• Manufacturer Part Number: PCA9574HR,115
• Description: IC I/O EXPANDER I2C 8B 16HXQFN
• Manufacturer: NXP Semiconductors

Specifications of PCA9574HR,115

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-XQFN (Exposed Pad), 16-eXQFN, 16-HXQFN
• Includes: POR
• Logic Family: CMOS
• Number Of Lines (input / Output): 8 / 8
• Operating Supply Voltage: 1.1 V to 3.6 V
• Power Dissipation: 75 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 1.1 V to 4.1 V
• Logic Type: I2C Bus Extender
• Maximum Clock Frequency: 400 KHz
• Maximum Operating Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8
• Number Of Output Lines: 8
• Output Current: +/- 5 mA
• Output Voltage: 1.1 V to 4.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4936-2

NXP Semiconductors
PCA9574_2
Product data sheet
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 11. Acknowledgement on the I
SCL from master
by transmitter
data output
by receiver
data output
Rev. 02 — 27 July 2009
condition
8-bit I
START
S
2
C-bus and SMBus, level translating, low voltage GPIO
2
C-bus
1
2
acknowledgement
not acknowledge
clock pulse for
acknowledge
8
PCA9574
© NXP B.V. 2009. All rights reserved.
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