PCA9574HR,115 NXP Semiconductors, PCA9574HR,115 Datasheet - Page 2

• Manufacturer Part Number: PCA9574HR,115
• Description: IC I/O EXPANDER I2C 8B 16HXQFN
• Manufacturer: NXP Semiconductors

Specifications of PCA9574HR,115

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-XQFN (Exposed Pad), 16-eXQFN, 16-HXQFN
• Includes: POR
• Logic Family: CMOS
• Number Of Lines (input / Output): 8 / 8
• Operating Supply Voltage: 1.1 V to 3.6 V
• Power Dissipation: 75 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 1.1 V to 4.1 V
• Logic Type: I2C Bus Extender
• Maximum Clock Frequency: 400 KHz
• Maximum Operating Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8
• Number Of Output Lines: 8
• Output Current: +/- 5 mA
• Output Voltage: 1.1 V to 4.1 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4936-2

NXP Semiconductors
2. Features
3. Applications
PCA9574_2
Product data sheet
The PCA9574 is available in TSSOP16, HVQFN16 and HXQFN16U packages and is
specified over the 40 C to +85 C industrial temperature range.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
400 kHz I
Compliant with I
Separate supply rails for core logic and I/O bank provides voltage level shifting
1.1 V to 3.6 V operation with level shifting feature
Very low standby current: < 1 A
8 configurable I/O pins that default to inputs at power-up
Outputs:
Inputs:
Active LOW reset (RESET) input pin resets device to power-up default state
GPIO All Call address allows programming of more than one device at the same time
with the same parameters
2 programmable slave addresses using 1 address pin
ESD protection exceeds 7000 V HBM per JESD22-A114, 500 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: TSSOP16, HVQFN16 and HXQFN16U
Cell phones
Media players
Multi voltage environments
Battery operated mobile gadgets
Motherboards
Servers
RAID systems
Industrial control
Medical equipment
PLCs
N
N
N
N
N
N
40 C to +85 C operation
Totem pole: 1 mA source and 3 mA sink
Independently programmable 100 k pull-up or pull-down for each I/O pin
Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
Programmable bus hold provides valid logic level when inputs are not actively
driven
Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change or to prevent spurious interrupts default to mask at
power-up
Polarity inversion register allows inversion of the polarity of the I/O pins when read
2
C-bus serial interface
2
C-bus Standard-mode (100 kHz)
Rev. 02 — 27 July 2009
8-bit I
2
C-bus and SMBus, level translating, low voltage GPIO
PCA9574
© NXP B.V. 2009. All rights reserved.
2 of 32