ADV7391BCPZ Analog Devices Inc, ADV7391BCPZ Datasheet - Page 15

• Manufacturer Part Number: ADV7391BCPZ
• Description: IC ENCODER VIDEO W/DAC 32-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7391BCPZ

• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LFCSP
• No. Of Pins: 32
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 85°C
• Operating: RoHS Compliant
• Input Format: Digital
• Output Format: Analogue
• Dac Resolution: 10bit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7391EBZ - BOARD EVAL FOR ADV7391 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIXEL PORT
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT*
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
Y OUTPUT
Y OUTPUT
SPECIFICATION SECTION OF THE DATA SHEET.
SPECIFICATION SECTION OF THE DATA SHEET.
HSYNC
VSYNC
HSYNC
VSYNC
Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
b
b
Rev. B | Page 15 of 108
a
a
ADV7390/ADV7391/ADV7392/ADV7393
Cb0
Y0
Cb0
Cr0
Y1
Y0
Cb2
Y2
Cr0
Cr2
Y3
Y1