PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 72

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
7.7
Data EEPROM memory has its own code-protect bits in
configuration
operations are disabled if either of these mechanisms
are enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 19.0
“Special Features of the CPU” for additional
information.
EXAMPLE 7-3:
TABLE 7-1:
DS39605C-page 70
INTCON
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Loop
Name
Operation During Code-Protect
CLRF
BCF
BCF
BCF
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
BCF
BSF
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
GIE/GIEH
OSCFIP
OSCFIF
OSCFIE
EEPGD
Bit 7
words.
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
EEADR
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
Loop
EECON1, WREN
INTCON, GIE
DATA EEPROM REFRESH ROUTINE
PEIE/GIEL TMR0IE
External
CFGS
Bit 6
—
—
—
read
Bit 5
—
—
—
—
and
FREE
INTE
EEIP
EEIE
Bit 4
EEIF
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
; Disable writes
; Enable interrupts
write
WRERR
RBIE
Bit 3
—
—
—
7.8
The data EEPROM is a high endurance, byte address-
able array that has been optimized for the storage of fre-
quently changing information (e.g., program variables or
other data that are updated often). Frequently changing
values will typically be updated more often than specifi-
cation D124. If this is not the case, an array refresh must
be performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
TMR0IF
WREN
LVDIP
LVDIF
LVDIE
Note:
Bit 2
Using the Data EEPROM
TMR3IP
TMR3IE
TMR3IF
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
Bit 1
INTF
WR
Bit 0
RBIF
RD
—
—
—
 2004 Microchip Technology Inc.
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xx-0 x000 uu-0 u000
1--1 -11- 1--1 -11-
0--0 -00- 0--0 -00-
0--0 -00- 0--0 -00-
POR, BOR
Value on:
—
Value on
all other
Resets
—