PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 173

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.0
PIC18F1220/1320 devices include several features
intended to maximize system reliability, minimize cost
through elimination of external components and offer
code protection. These are:
• Oscillator Selection
• Resets:
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
Several oscillator options are available to allow the part
to fit the application. The RC oscillator option saves
system cost, while the LP crystal option saves power.
These are discussed in detail in Section 2.0 “Oscillator
Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F1220/1320 devices
have a Watchdog Timer, which is either permanently
enabled via the configuration bits, or software
controlled (if configured as disabled).
TABLE 19-1:
 2004 Microchip Technology Inc.
300001h
300002h
300003h
300005h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
File Name
SPECIAL FEATURES OF
THE CPU
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3H MCLRE
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
x = unknown, u = unchanged, – = unimplemented. Shaded cells are unimplemented, read as ‘0’.
See Register 19-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
CONFIGURATION BITS AND DEVICE IDS
(1)
(1)
DEBUG
DEV10
WRTD
DEV2
IESO
Bit 7
CPD
—
—
—
—
—
—
EBTRB
WRTB
FSCM
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
—
—
WRTC
DEV0
DEV8
Bit 5
—
—
—
—
—
—
—
—
—
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
—
—
FOSC3
BORV1
REV3
DEV6
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate configuration register bits.
19.1
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
Programming the configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
configuration register. In normal operation mode, a
TBLWT instruction, with the TBLPTR pointing to the
configuration register, sets up the address and the data
for the configuration register write. Setting the WR bit
starts a long write to the configuration register. The con-
figuration registers are written a byte at a time. To write
or erase a configuration cell, a TBLWT instruction can
write a ‘1’ or a ‘0’ into the cell. For additional details on
Flash programming, refer to Section 6.5 “Writing to
Flash Program Memory”.
Bit 3
—
—
—
—
—
—
—
—
Configuration Bits
FOSC2
BORV0
PIC18F1220/1320
REV2
DEV5
Bit 2
LVP
—
—
—
—
—
—
—
FOSC1
EBTR1
WRT1
REV1
DEV4
Bit 1
BOR
CP1
—
—
—
—
—
PWRTEN
FOSC0
EBTR0
WRT0
STVR
REV0
DEV3
Bit 0
WDT
CP0
—
—
—
—
DS39605C-page 171
Unprogrammed
11-- 1111
---- 1111
---1 1111
1--- ----
1--- -1-1
---- --11
11-- ----
---- --11
111- ----
---- --11
-1-- ----
xxxx xxxx
0000 0111
Default/
Value
(1)