PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 182

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
19.2
For PIC18F1220/1320 devices, the WDT is driven by the
INTRC source. When the WDT is enabled, the clock
source is also enabled. The nominal WDT period is 4 ms
and has the same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is selected
by a multiplexer, controlled by bits in Configuration
Register 2H. Available periods range from 4 ms to
131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: execute a SLEEP or CLRWDT instruction, the IRCF
bits (OSCCON<6:4>) are changed or a clock failure has
occurred.
Adjustments to the internal oscillator clock period using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
FIGURE 19-1:
REGISTER 19-14: WDTCON REGISTER
DS39605C-page 180
INTRC Oscillator
WDTPS<3:0>
Watchdog Timer (WDT)
All Device
SWDTEN
(31 kHz)
WDTEN
CLRWDT
bit 7-1
bit 0
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
Resets
Sleep
WDT BLOCK DIAGRAM
bit 7
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note:
U-0
—
Enable WDT
This bit has no effect if the configuration bit, WDTEN (CONFIG2H<0>), is enabled.
WDT Counter
U-0
—
125
W = Writable bit
INTRC Control
4
Programmable Postscaler
U-0
—
1:1 to 1:32,768
U-0
—
19.2.1
Register 19-14 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only if the configuration bit has
disabled the WDT.
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed
-n = Value at POR
WDT
U-0
—
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
Reset
U-0
—
 2004 Microchip Technology Inc.
U-0
—
WDT
Reset
Wake-up
from Sleep
SWDTEN
R/W-0
bit 0