PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 145

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

16.3.2
The receiver block diagram is shown in Figure 16-5.
The data is received on the RB4/AN6/RX/DT/KBI0 pin
and drives the data recovery block. The data recovery
block is actually a high-speed shifter, operating at x16
times the baud rate, whereas the main receive serial
shifter operates at the bit rate or at F
would typically be used in RS-232 systems.
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using interrupts, ensure that the GIE and PEIE
FIGURE 16-5:
 2004 Microchip Technology Inc.
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
Enable the reception by setting bit CREN.
Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
RB4/AN6/RX/DT/KBI0
EUSART ASYNCHRONOUS
RECEIVER
BRG16
EUSART RECEIVE BLOCK DIAGRAM
SPBRGH
Baud Rate Generator
x64 Baud Rate CLK
and Control
Pin Buffer
SPEN
SPBRG
OSC
. This mode
Recovery
Interrupt
Data
or
or
64
16
4
CREN
16.3.3
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
Read RCREG to determine if the device is being
addressed.
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
RX9
PIC18F1220/1320
Stop
MSb
RCIF
RCIE
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
RX9D
(8)
OERR
7
RSR Register
RCREG Register
8
Data Bus
1
FERR
DS39605C-page 143
0
LSb
Start
FIFO