PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet - Page 114

• Manufacturer Part Number: PIC18F1320-I/SO
• Description: Microcontroller; 8 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-PDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1320-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 8K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F1220/1320
14.1
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
FIGURE 14-1:
FIGURE 14-2:
DS39605C-page 112
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set TMR3IF Flag bit
on Overflow
T1OSO/
T13CKI
T1OSI
Timer3 Operation
T1OSO/
T13CKI
T1OSI
Data Bus<7:0>
TMR3IF
Overflow
Interrupt
Flag bit
Write TMR3L
Read TMR3L
TIMER3 BLOCK DIAGRAM
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
T1OSC
TMR3H
T1OSC
8
High Byte
TMR3H
Timer3
8
To Timer1 Clock Input
Oscillator
Enable
T1OSCEN
8
TMR3L
Oscillator
Enable
T1OSCEN
TMR3
(1)
CLR
8
TMR3L
(1)
Clock
Internal
F
OSC
CLR
/4
TMR3ON
On/Off
TMR3CS
F
Internal
Clock
CCP Special Event Trigger
T3CCPx
1
0
OSC
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/PGC/
T1OSO/T13CKI/P1C/KBI2 pins become inputs. That
is, the TRISB7:TRISB6 value is ignored and the pins
are read as ‘0’.
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
/4
TMR3ON
T3CKPS1:T3CKPS0
On/Off
TMR3CS
T3SYNC
Prescaler
1, 2, 4, 8
1
0
T3CCPx
CCP Special Event Trigger
0
1
T3CKPS1:T3CKPS0
2
T3SYNC
Prescaler
1, 2, 4, 8
0
1
Peripheral Clocks
Synchronized
 2004 Microchip Technology Inc.
2
Clock Input
Synchronize
det
Synchronized
Clock Input
Synchronize
Peripheral
Clocks
det