PIC12F675-E/P Microchip Technology Inc., PIC12F675-E/P Datasheet - Page 44

• Manufacturer Part Number: PIC12F675-E/P
• Description: 8 PIN, 1.75 KB FLASH, 64 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F675-E/P

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F629/675
TABLE 7-1:
7.1.5
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled).
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
ADRESH:ADRESL registers will retain the value of the
FIGURE 7-2:
DS41190C-page 42
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical T
Operation
16 T
32 T
64 T
A/D RC
(ADFM = 0)
(ADFM = 1)
2 T
4 T
8 T
A/D Clock Source (T
2: These values violate the minimum required T
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
OSC
OSC
OSC
OSC
OSC
OSC
conversion
conversion will be performed during SLEEP.
STARTING A CONVERSION
T
ADCS2:ADCS0
AD
MSB
10-BIT A/D RESULT FORMAT
Bit 7
Bit 7
vs. DEVICE OPERATING FREQUENCIES
000
100
001
101
010
110
x11
sample.
Unimplemented: Read as ‘0
AD
)
Instead,
ADRESH
2 - 6 µs
100 ns
200 ns
400 ns
800 ns
20 MHz
1.6 µs
3.2 µs
10-bit A/D Result
AD
(1,4)
time of 4 µs for V
(2)
(2)
(2)
(2)
the
MSB
AD
time.
Bit 0
Bit 0
2 - 6 µs
12.8 µs
400 ns
800 ns
previous conversion. After an aborted conversion, a
2 T
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
7.1.6
The A/D conversion can be supplied in two formats: left
or right shifted. The ADFM bit (ADCON0<7>) controls
the output format. Figure 7-2 shows the output formats.
5 MHz
1.6 µs
3.2 µs
6.4 µs
DD
Note:
AD
Device Frequency
> 3.0V.
(1,4)
(2)
(2)
(3)
delay is required before another acquisition can
Bit 7
Bit 7
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
CONVERSION OUTPUT
10-bit A/D Result
LSB
2 - 6 µs
16.0 µs
500 ns
1.0 µs
8.0 µs
4 MHz
2.0 µs
4.0 µs
Unimplemented: Read as ‘0’
 2003 Microchip Technology Inc.
ADRESL
(2)
(3)
(1,4)
(2)
(3)
2 - 6 µs
1.25 MHz
12.8 µs
25.6 µs
51.2 µs
1.6 µs
3.2 µs
6.4 µs
Bit 0
Bit 0
LSB
(1,4)
(3)
(3)
(3)