PIC12F675-E/P Microchip Technology Inc., PIC12F675-E/P Datasheet - Page 33

• Manufacturer Part Number: PIC12F675-E/P
• Description: 8 PIN, 1.75 KB FLASH, 64 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F675-E/P

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.1
Timer1 can operate in one of three modes:
• 16-bit timer with prescaler
• 16-bit synchronous counter
• 16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every
instruction cycle. In Counter mode, Timer1 is incre-
mented on the rising edge of the external clock input
T1CKI. In addition, the Counter mode clock can be
synchronized to the microcontroller system clock or
run asynchronously.
In Counter and Timer modules, the counter/timer clock
can be gated by the T1G input.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
FIGURE 5-2:
 2003 Microchip Technology Inc.
Note:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
Timer1 Modes of Operation
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
clock.
TIMER1 INCREMENTING EDGE
5.2
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
• Timer1 interrupt Enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
• GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
5.3
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
Note:
Timer1 Interrupt
Timer1 Prescaler
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
PIC12F629/675
DS41190C-page 31