PIC12F675-E/P Microchip Technology Inc., PIC12F675-E/P Datasheet - Page 23

• Manufacturer Part Number: PIC12F675-E/P
• Description: 8 PIN, 1.75 KB FLASH, 64 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F675-E/P

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.2.2
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR'd
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
REGISTER 3-4:
 2003 Microchip Technology Inc.
bit 7-6
bit 5-0
INTERRUPT-ON-CHANGE
IOC — INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
bit 7
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-Change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be
Legend:
R = Readable bit
- n = Value at POR
U-0
—
recognized.
U-0
—
R/W-0
IOC5
W = Writable bit
’1’ = Bit is set
R/W-0
IOC4
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
Note:
Any read or write of GPIO. This will end the
mismatch condition.
Clear the flag bit GPIF.
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
IOC3
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
PIC12F629/675
R/W-0
IOC2
x = Bit is unknown
R/W-0
IOC1
DS41190C-page 21
R/W-0
IOC0
bit 0