PIC12F675-E/P Microchip Technology Inc., PIC12F675-E/P Datasheet - Page 35

• Manufacturer Part Number: PIC12F675-E/P
• Description: 8 PIN, 1.75 KB FLASH, 64 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F675-E/P

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.4
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software
(Section 5.4.1).
5.4.1
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PICmicro™ Mid-Range
MCU Family Reference Manual (DS33023) show how
to read and write Timer1 when it is running in
Asynchronous mode.
TABLE 5-1:
 2003 Microchip Technology Inc.
0Bh/8Bh INTCON
0Ch
0Eh
0Fh
10h
8Ch
Legend:
Address
Note:
Timer1 Operation in
Asynchronous Counter Mode
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
PIR1
TMR1L
TMR1H
T1CON
PIE1
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
are
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC12F675.
Name
needed
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Bit 7
EEIF
EEIE
GIE
—
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
to
PEIE
ADIF
ADIE
Bit 6
read/write
Bit 5
T0IE
—
—
the
INTE
Bit 4
timer
—
—
CMIE
GPIE
CMIF
Bit 3
5.5
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low power oscillator rated up to 37 kHz. It
will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 9-2 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the system clock is derived from the internal oscillator.
As with the system LP oscillator, the user must provide
a software time delay to ensure proper oscillator
start-up
While enabled, TRISIO4 and TRISIO5 are set. GP4
and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read
‘1’.
5.6
Timer1 can only operate during SLEEP when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine on an overflow.
Note:
Bit 2
T0IF
—
—
Timer1 Oscillator
Timer1 Operation During SLEEP
The oscillator requires a start-up and stabi-
lization time before use. Thus, T1OSCEN
should be set and a suitable delay
observed prior to enabling Timer1.
Bit 1
INTF
PIC12F629/675
—
—
TMR1IF 00-- 0--0 00-- 0--0
TMR1IE 00-- 0--0 00-- 0--0
GPIF
Bit 0
0000 0000 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOD
Value on
DS41190C-page 33
Value on
RESETS
all other