PIC18F452-I/PT Microchip Technology Inc., PIC18F452-I/PT Datasheet - Page 89

• Manufacturer Part Number: PIC18F452-I/PT
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.0
Depending on the device selected, there are either five
ports or three ports available. Some pins of the I/O
ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when
a peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
• LAT register (output latch)
The data latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
9.1
PORTA is a 7-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register reads and writes the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
The other PORTA pins are multiplexed with analog
inputs and the analog V
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
© 2006 Microchip Technology Inc.
device)
Note:
I/O PORTS
PORTA, TRISA and LATA
Registers
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA6 and RA4 are configured as
digital inputs.
REF
+ and V
REF
- inputs. The
EXAMPLE 9-1:
FIGURE 9-1:
CLRF PORTA
CLRF LATA
MOVLW 0x07
MOVWF ADCON1
MOVLW 0xCF
MOVWF TRISA
WR TRISA
Note 1:
WR LATA
or
PORTA
Data
Bus
RD PORTA
To A/D Converter and LVD Modules
SS Input (RA5 only)
I/O pins have protection diodes to V
TRIS Latch
Data Latch
D
D
CK
CK
RD LATA
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; Value used to
Q
Q
INITIALIZING PORTA
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
Q
Q
RD TRISA
PIC18FXX2
Q
Analog
Input
Mode
EN
D
DS39564C-page 87
DD
V
V
N
P
SS
DD
and V
TTL
Input
Buffer
I/O pin
SS
.
(1)