PIC18F452-I/PT Microchip Technology Inc., PIC18F452-I/PT Datasheet - Page 189

• Manufacturer Part Number: PIC18F452-I/PT
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

17.4
Figure 17-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
FIGURE 17-3:
17.4.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
FIGURE 17-4:
© 2006 Microchip Technology Inc.
A/D Conversions
T
CY
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D RESULT REGISTERS
- T
AD
7
Conversion Starts
0000 00
ADRESH
T
b9
AD
A/D CONVERSION T
A/D RESULT JUSTIFICATION
1 T
Right Justified
AD
b8
2 1 0 7
ADFM = 1
2 T
AD
b7
10-bit Result
3 T
ADRESL
AD
b6
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
4 T
AD
AD
b5
0
5 T
CYCLES
ADIF bit is set, holding capacitor is connected to analog input.
10-bit Result
AD
b4
6 T
AD
b3
7 T
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2 T
is required before the next acquisition is started. After
this 2 T
automatically started. The GO/DONE bit can then be
set to start the conversion.
Format Select bit (ADFM) controls this justification.
Figure 17-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s. When an
A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general
purpose 8-bit registers.
Note:
AD
b2
7
8
AD
ADRESH
T
AD
wait, acquisition on the selected channel is
b1
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
10-bit Result
9 T
AD
ADFM = 0
b0
Left Justified
10
0 7 6 5
T
AD
b0
PIC18FXX2
ADRESL
11
0000 00
DS39564C-page 187
0
AD
wait