PIC18F452-I/PT Microchip Technology Inc., PIC18F452-I/PT Datasheet - Page 121

• Manufacturer Part Number: PIC18F452-I/PT
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

14.3
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 or TMR3 registers when an
event occurs on pin RC2/CCP1. An event is defined as
one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set; it must be
cleared in software. If another capture occurs before the
value in register CCPR1 is read, the old captured value
is overwritten by the new captured value.
14.3.1
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
14.3.2
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with each CCP module is
selected in the T3CON register.
FIGURE 14-1:
© 2006 Microchip Technology Inc.
Note:
Capture Mode
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
CCP PIN CONFIGURATION
TIMER1/TIMER3 MODE SELECTION
CCP1 pin
CCP2 pin
CAPTURE MODE OPERATION BLOCK DIAGRAM
Q’s
Q’s
Edge Detect
Edge Detect
Prescaler
Prescaler
1, 4, 16
1, 4, 16
and
and
CCP1CON<3:0>
CCP2CON<3:0>
Set Flag bit CCP2IF
Set Flag bit CCP1IF
T3CCP1
T3CCP2
T3CCP2
T3CCP1
T3CCP2
T3CCP2
14.3.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in Operating mode.
14.3.4
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 14-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 14-1:
CLRF
MOVLW
MOVWF
NEW_CAPT_PS ; Load WREG with the
CCP1CON
CCP1CON, F ; Turn CCP module off
SOFTWARE INTERRUPT
CCP PRESCALER
TMR1
Enable
TMR1
Enable
TMR3
Enable
TMR3
Enable
CCPR1H
CCPR2H
TMR1H
TMR1H
TMR3H
TMR3H
CHANGING BETWEEN
CAPTURE PRESCALERS
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
PIC18FXX2
CCPR1L
CCPR2L
TMR3L
TMR1L
TMR3L
TMR1L
DS39564C-page 119