PIC18F452-I/PT Microchip Technology Inc., PIC18F452-I/PT Datasheet - Page 160

• Manufacturer Part Number: PIC18F452-I/PT
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18FXX2
15.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (T
SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for T
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 15-23).
15.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t occur).
FIGURE 15-23:
FIGURE 15-24:
DS39564C-page 158
ACKNOWLEDGE SEQUENCE
TIMING
Note: T
Note: T
SCL
SDA
WCOL Status Flag
BRG
sequence
Falling edge of
9th clock
SSPIF
Write to SSPCON2
Acknowledge sequence starts here,
SDA
BRG
SCL
BRG
. The SCL pin is then pulled low. Fol-
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
= one baud rate generator period.
ACK
= one baud rate generator period.
Set SSPIF at the end
of receive
Set PEN
ACKEN = 1, ACKDT = 0
enable
Write to SSPCON2
T
T
BRG
BRG
bit,
SDA asserted low before rising edge of clock
to setup STOP condition.
BRG
8
D0
) and the
ACKEN
T
SCL brought high after T
BRG
Cleared in
software
P
T
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
BRG
T
BRG
ACK
15.4.13
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the STOP sequence enable
bit, PEN (SSPCON2<2>). At the end of a receive/trans-
mit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low. When the SDA line is sampled
low, the baud rate generator is reloaded and counts
down to 0. When the baud rate generator times out, the
SCL pin will be brought high, and one T
generator rollover count) later, the SDA pin will be
de-asserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A T
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 15-24).
15.4.13.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
PEN bit (SSPCON2<2>) is cleared by
T
hardware and the SSPIF bit is set
BRG
9
BRG
BRG
Set SSPIF at the end
of Acknowledge sequence
, followed by SDA = 1 for T
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
© 2006 Microchip Technology Inc.
Cleared in
software
BRG
BRG
(baud rate
BRG