PIC18F452-I/PT Microchip Technology Inc., PIC18F452-I/PT Datasheet - Page 156

• Manufacturer Part Number: PIC18F452-I/PT
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18FXX2
15.4.9
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I
logic module is in the IDLE state. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sampled low, the baud rate generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (T
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is reloaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL must be sampled high for one T
then followed by assertion of the SDA pin (SDA = 0) for
one T
bit (SSPCON2<1>) will be automatically cleared and
the baud rate generator will not be reloaded, leaving
the SDA pin held low. As soon as a START condition is
detected on the SDA and SCL pins, the S bit
(SSPSTAT<3>) will be set. The SSPIF bit will not be set
until the baud rate generator has timed out.
FIGURE 15-20:
DS39564C-page 154
Note 1: If RSEN is programmed while any other
BRG ,
2: A bus collision during the Repeated
while SCL is high. Following this, the RSEN
I
START CONDITION TIMING
event is in progress, it will not take effect.
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
2
START condition occurs if:
C MASTER MODE REPEATED
from low to high.
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
BRG
Falling edge of ninth clock
). When the baud rate generator
REPEAT START CONDITION WAVEFORM
SDA
SCL
End of Xmit
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change)
BRG
. This action is
2
C
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
15.4.9.1
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Sr = Repeated START
T
BRG
At completion of START bit,
hardware clear RSEN bit
Set S (SSPSTAT<3>)
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
and set SSPIF
Write to SSPBUF occurs here
WCOL Status Flag
T
BRG
1st bit
T
BRG
© 2006 Microchip Technology Inc.