PIC18F452-I/PT Microchip Technology Inc., PIC18F452-I/PT Datasheet - Page 49

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PIC18F452-I/PT

Manufacturer Part Number
PIC18F452-I/PT
Description
44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F452-I/PT

A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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TABLE 4-2:
© 2006 Microchip Technology Inc.
OSCCON
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
TMR3H
TMR3L
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
Legend:
Note 1:
File Name
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers and bits are reserved on the PIC18F2X2 devices; always maintain these clear.
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes.
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register1 High Byte
Capture/Compare/PWM Register1 Low Byte
Capture/Compare/PWM Register2 High Byte
Capture/Compare/PWM Register2 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
USART1 Baud Rate Generator
USART1 Receive Register
USART1 Transmit Register
Data EEPROM Address Register
Data EEPROM Data Register
Data EEPROM Control Register 2 (not a physical register)
EEPGD
ADCS1
WCOL
GCEN
ADFM
CSRC
SPEN
RD16
RD16
IPEN
Bit 7
SMP
REGISTER FILE SUMMARY (CONTINUED)
TOUTPS3
ACKSTAT
T3CCP2
SSPOV
ADCS0
ADCS2
CFGS
Bit 6
CKE
RX9
TX9
2
T1CKPS1
TOUTPS2
T3CKPS1
C Slave mode. SSP Baud Rate Reload Register in I
SSPEN
ACKDT
DC1B1
DC2B1
IRVST
CHS2
TXEN
SREN
Bit 5
D/A
TOUTPS1
T1CKPS0
T3CKPS0
ACKEN
LVDEN
DC1B0
DC2B0
SYNC
CREN
CHS1
FREE
Bit 4
CKP
RI
P
T1OSCEN
TOUTPS0
CCP1M3
CCP2M3
T3CCP1
WRERR
SSPM3
ADDEN
PCFG3
LVDL3
RCEN
CHS0
Bit 3
TO
S
GO/DONE
TMR2ON
CCP1M2
CCP2M2
T1SYNC
T3SYNC
SSPM2
PCFG2
LVDL2
BRGH
WREN
FERR
Bit 2
R/W
PEN
PD
T2CKPS1
2
TMR1CS
TMR3CS
CCP1M1
CCP2M1
C Master mode.
SSPM1
PCFG1
LVDL1
OERR
RSEN
TRMT
Bit 1
POR
WR
UA
T2CKPS0 -000 0000
TMR1ON 0-00 0000
TMR3ON 0000 0000
CCP1M0 --00 0000
CCP2M0 --00 0000
PIC18FXX2
SWDTE
SSPM0
PCFG0
LVDL0
ADON
RX9D
TX9D
Bit 0
BOR
SCS
SEN
RD
BF
---- ---0
--00 0101
---- ---0
0--1 11qq 53, 28, 84
xxxx xxxx
xxxx xxxx
0000 0000
1111 1111
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx 187,188
xxxx xxxx 187,188
0000 00-0
00-- 0000
xxxx xxxx 121, 123
xxxx xxxx 121, 123
xxxx xxxx 121, 123
xxxx xxxx 121, 123
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000 175, 178,
0000 0000 173, 176,
0000 -010
0000 000x
0000 0000
0000 0000
---- ----
xx-0 x000
POR, BOR
Value on
DS39564C-page 47
on page:
Details
65, 69
65, 69
191
203
107
107
107
125
134
126
127
137
181
182
168
180
179
166
167
111
112
111
117
117
113
113
113
21
69
66

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