DP83907VF National Semiconductor, DP83907VF Datasheet - Page 23

• Manufacturer Part Number: DP83907VF
• Description: IC CONTROLLR AT/LANII TP 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83907VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83907VF

0–2
3–5
Bit
5 0 Register Descriptions
5 1 CONFIGURATION REGISTERS
These registers are used to configure the operation of the DP83907 typically after power up These registers control the
configuration of bus interface setting options like interrupt selection I O base address and other specific modes
MODE CONFIGURATION REGISTER A
To prevent any accidental writes of this register it is ‘‘hidden’’ behind a previously unused register Register 0AH in the
DP83907’s Page 0 of registers was previously reserved on a read Now Configuration Register A can be read at that address
and can be written to by following a read to 0AH with a write to 0AH If any other DP83907 register accesses take place between
the read and the write then the write to 0AH will access the Remote Byte Count Register 0
6
7
IOAD0–IOAD2
INT0–INT2
FRd WR
Symbol
RES
I O ADDRESS These three bits determine the base I O address of the DP83907 within the system’s
I O map The DP83907 occupies 20H bytes of the system’s address space
Bit 2 1 0
Note 1 When 001 is selected the DP83907 will not respond to any I O Addresses but will allow 4 consecutive writes to 278H to
write these three bits of this register This sequence will only operate once after a power-on reset This mode allows the DP83907
to be configured via software without conflicting with other peripherals
INTERRUPT LINE USED
Bit 5 4 3
FAST RD WR When this bit is set high the DP83907 in I O mode will begin the next port fetch
before the current IORD IOWR has completed In slow ISA systems this may cause the data in the
port to be overwritten before the ISA cycle has been completed
RESERVED This bit must be set low for normal operation
RES
7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
FRd Wr
0300H
Software (Note 1)
0240H
0280H
02C0H
0320H
0340H
0360H
IRQ
10
11
12
15
6
3
4
5
9
INT2
5
INT1
4
23
INT0
3
Function
IOAD2
2
IOAD1
1
IOAD0
0