ENC28J60-I/SO Microchip Technology, ENC28J60-I/SO Datasheet - Page 78

• Manufacturer Part Number: ENC28J60-I/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SO

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.1 V to 3.6 V
• Supply Current (max): 180 mA
• Data Rate: 10Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: SPI
• Supply Current: 180mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Ethernet Connection Type: 10Base-T
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC28J60
15.1
When the BIST controller is started, it will fill the entire
buffer with the data generated for the current test
configuration and it will also calculate a checksum of
the data as it is written. When the BIST is complete, the
EBSTCS registers will be updated with the checksum.
The host controller will be able to determine if the test
passed or failed by using the DMA module to calculate
a checksum of all memory. The resulting checksum
generated by the DMA should match the BIST check-
sum. If after any properly executed test, the checksums
differ, a hardware fault may be suspected.
The BIST controller supports 3 different operations:
• Random Data Fill
• Address Fill
• Pattern Shift Fill
The ports through which the BIST and DMA modules
access the dual port SRAM can be swapped for each
of the four Test modes to ensure proper read/write
capability from both ports.
To use the BIST:
1.
2.
3.
4.
5.
6.
7.
8.
9.
To ensure full testing, the test should be redone with
the Port Select bit, PSEL, altered. When not using
Address Fill mode, additional tests may be done with
different seed values to gain greater confidence that
the memory is working as expected.
DS39662B-page 76
Program the EDMAST register pair to 0000h.
Program EDMAND and ERXND register pairs to
1FFFh.
Configure the DMA for checksum generation by
setting CSUMEN in ECON1.
Write the seed/initial shift value byte to the
EBSTSD register (this is not necessary if
Address Fill mode is used).
Enable Test mode, select the desired test, select
the desired port configuration for the test.
Start the BIST by setting EBSTCON.BISTST.
Start the DMA checksum by setting DMAST in
ECON1. The DMA controller will read the
memory at the same rate the BIST controller will
write to it, so the DMA can be started any time
after the BIST is started.
Wait for the DMA to complete by polling the
DMAST bit or receiving the DMA interrupt (if
enabled).
Compare the EDMACS registers with the
EBSTCS registers.
Using the BIST
Preliminary
At any time during a test, the test can be canceled by
clearing the BISTST, DMAST and TME bits. While the
BIST is filling memory, the EBSTSD register should not
be accessed, nor should any configuration changes
occur. When the BIST completes its memory fill and
checksum generation, the BISTST bit will automatically
be cleared.
The BIST module requires one main clock cycle for
each byte that it writes into the RAM. The DMA mod-
ule’s checksum implementation requires the same time
but it can be started immediately after the BIST is
started. As a result, the minimum time required to do
one test pass is slightly greater than 327.68 s.
15.2
In Random Data Fill mode, the BIST controller will write
pseudo-random data into the buffer. The random data
is generated by a Linear Feedback Shift Register
(LFSR) implementation. The random number genera-
tor is seeded by the initial contents of the EBSTSD
register and the register will have new contents when
the BIST is finished.
Because of the LFSR implementation, an initial seed of
zero will generate a continuous pattern of zeros. As a
result, a non-zero seed value will likely perform a more
extensive memory test. Selecting the same seed for
two separate trials will allow a repeat of the same test.
15.3
In Address Fill mode, the BIST controller will write the
low byte of each memory address into the associated
buffer location. As an example, after the BIST is oper-
ated, the location 0000h should have 00h in it, location
0001h should have 01h in it, location 0E2Ah should
have 2Ah in it and so on. With this fixed memory
pattern, the BIST and DMA modules should always
generate a checksum of F807h. The host controller
may use Address Fill mode to confirm that the BIST
and DMA modules themselves are both operating as
intended.
15.4
In Pattern Shift Fill mode, the BIST controller writes the
value of EBSTSD into memory location 0000h. Before
writing to location 0001h, it shifts the contents of
EBSTSD to the left by the value specified by the
PSV2:PSV0 bits in EBSTCON. Bits that leave the most
significant end of EBSTSD are wrapped around to the
least significant side. This shift is repeated for each
new address. As a result of shifting the data, a checker-
board pattern can be written into the buffer memory to
confirm that adjacent memory elements do not affect
each other when accessed.
Random Data Fill Mode
Address Fill Mode
Pattern Shift Fill Mode
© 2006 Microchip Technology Inc.