ENC28J60-I/SO Microchip Technology, ENC28J60-I/SO Datasheet - Page 26

• Manufacturer Part Number: ENC28J60-I/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SO

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.1 V to 3.6 V
• Supply Current (max): 180 mA
• Data Rate: 10Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: SPI
• Supply Current: 180mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Ethernet Connection Type: 10Base-T
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC28J60
REGISTER 3-6:
DS39662B-page 24
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8-6
bit 5
bit 4-0
Note 1:
U-0
U-0
—
—
Reset values of the Duplex mode/status bit depends on the connection of the LED to the LEDB pin (see
Section 2.6 “LED Configuration” for additional details).
Unimplemented: Read as ‘0’
TXSTAT: PHY Transmit Status bit
1 = PHY is transmitting data
0 = PHY is not transmitting data
RXSTAT: PHY Receive Status bit
1 = PHY is receiving data
0 = PHY is not receiving data
COLSTAT: PHY Collision Status bit
1 = A collision is occuring
0 = A collision is not occuring
LSTAT: PHY Link Status bit (non-latching)
1 = Link is up
0 = Link is down
DPXSTAT: PHY Duplex Status bit
1 = PHY is configured for full-duplex operation (PHCON1<8> is set)
0 = PHY is configured for half-duplex operation (PHCON1<8> is clear)
Unimplemented: Read as ‘0’
PLRITY: Polarity Status bit
1 = The polarity of the signal on TPIN+/TPIN- is reversed
0 = The polarity of the signal on TPIN+/TPIN- is correct
Unimplemented: Read as ‘0’
U-0
U-0
—
—
PHSTAT2: PHYSICAL LAYER STATUS REGISTER 2
W = Writable bit
‘1’ = Bit is set
TXSTAT
PLRITY
R-0
R-0
RXSTAT
(1)
R-0
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
COLSTAT
R-0
U-0
—
LSTAT
R-0
U-0
—
© 2006 Microchip Technology Inc.
x = Bit is unknown
DPXSTAT
U-0
R-x
—
(1)
U-0
U-0
—
—
bit 8
bit 0