ENC28J60-I/SO Microchip Technology, ENC28J60-I/SO Datasheet - Page 41

• Manufacturer Part Number: ENC28J60-I/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SO

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.1 V to 3.6 V
• Supply Current (max): 180 mA
• Data Rate: 10Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: SPI
• Supply Current: 180mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Ethernet Connection Type: 10Base-T
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.0
7.1
The MAC inside the ENC28J60 will automatically gener-
ate the preamble and start-of-frame delimiter fields when
transmitting. Additionally, the MAC can generate any
padding (if needed) and the CRC if configured to do so.
The host controller must generate and write all other
frame fields into the buffer memory for transmission.
FIGURE 7-1:
© 2006 Microchip Technology Inc.
bit 7-4
bit 3
bit 2
bit 1
bit 0
TRANSMITTING AND
RECEIVING PACKETS
Transmitting Packets
Unused
PHUGEEN: Per Packet Huge Frame Enable bit
When POVERRIDE = 1:
1 = The packet will be transmitted in whole
0 = The MAC will transmit up to the number of bytes specified by MAMXFL. If the packet is larger
When POVERRIDE = 0:
This bit is ignored.
PPADEN: Per Packet Padding Enable bit
When POVERRIDE = 1:
1 = The packet will be zero padded to 60 bytes if it is less than 60 bytes
0 = The packet will be trasmitted without adding any padding bytes
When POVERRIDE = 0:
This bit is ignored.
PCRCEN: Per Packet CRC Enable bit
When POVERRIDE = 1:
1 = A valid CRC will be calculated and attached to the frame
0 = No CRC will be appended. The last 4 bytes of the frame will be checked for validity as a
When POVERRIDE = 0:
This bit is ignored.
POVERRIDE: Per Packet Override bit
1 = The values of PCRCEN, PPADEN and PHUGEEN will override the configuration defined by
0 = The values in MACON3 will be used to determine how the packet will be transmitted
bit 7
—
than MAMXFL, it will be aborted after MAMXFL is reached.
CRC.
MACON3
FORMAT FOR PER PACKET CONTROL BYTES
—
—
—
Preliminary
PHUGEEN
Additionally, the ENC28J60 requires a single per packet
control byte to precede the packet for transmission. The
per packet control byte is organized as shown in
Figure 7-1. Before transmitting packets, the MAC
registers which alter the transmission characteristics
should be initialized as documented in Section 6.0
“Initialization”.
For an example of how the entire transmit packet and
results will look in memory, see Figure 7-2.
PPADEN
PCRCEN
ENC28J60
POVERRIDE
DS39662B-page 39
bit 0