ENC28J60-I/SO Microchip Technology, ENC28J60-I/SO Datasheet - Page 74

• Manufacturer Part Number: ENC28J60-I/SO
• Description: IC ETHERNET CTRLR W/SPI 28SOIC
• Manufacturer: Microchip Technology

Specifications of ENC28J60-I/SO

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: Ethernet Controller, MAC/10Base-T
• Interface: SPI
• Voltage - Supply: 3.1 V ~ 3.6 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.1 V to 3.6 V
• Supply Current (max): 180 mA
• Data Rate: 10Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3
• Interface Type: SPI
• Supply Current: 180mA
• Supply Voltage Range: 3.1V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Ethernet Connection Type: 10Base-T
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC28J60
13.2
The checksum calculation logic treats the source data as
a series of 16-bit big-endian integers. If the source range
contains an odd number of bytes, a padding byte of 00h
is effectively added to the end of the series for purposes
of calculating the checksum. The calculated checksum
is the 16-bit one’s complement of the one’s complement
sum of all 16-bit integers. For example, if the bytes
included in the checksum were {89h, ABh, CDh}, the
checksum would begin by computing 89ABh + CD00h.
A carry out of the 16th bit would occur in the example, so
in 16-bit one’s complement arithmetic, it would be added
back to the first bit. The resulting value of 56ACh would
finally be complemented to achieve a checksum of
A953h.
To calculate a checksum:
1.
2.
3.
When the checksum is finished being calculated, the
hardware will clear the DMAST bit, set the DMAIF bit
and an interrupt will be generated if enabled. The DMA
TABLE 13-1:
DS39662B-page 72
EIE
EIR
ECON1
ERXNDL
ERXNDH
EDMASTL
EDMASTH
EDMANDL
EDMANDH
EDMADSTL DMA Destination Low Byte (EDMADST<7:0>)
EDMADSTH
EDMACSL
EDMACSH
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the DMA controller.
Register
Name
Program the EDMAST and EDMAND register
pairs to point to the first and last bytes of buffer
data to be included in the checksum. Care should
be taken when programming these Pointers to
prevent a never ending checksum calculation
due to receive buffer wrapping.
To generate an optional interrupt when the
checksum calculation is done, clear EIR.DMAIF,
set EIE.DMAIE and set EIE.INTIE.
Start the calculation by setting ECON1.CSUMEN
and ECON1.DMAST.
Checksum Calculations
RX End Low Byte (ERXND<7:0>)
DMA Start Low Byte (EDMAST<7:0>)
DMA End Low Byte (EDMAND<7:0>)
DMA Checksum Low Byte (EDMACS<7:0>)
DMA Checksum High Byte (EDMACS<15:8>)
TXRST
INTIE
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER
—
—
—
—
—
RXRST
PKTIE
PKTIF
Bit 6
—
—
—
—
DMAST
DMAIE
DMAIF
Bit 5
—
—
—
—
RX End High Byte (ERXND<12:8>)
DMA Start High Byte (EDMAST<12:8>)
DMA End High Byte (EDMAND<12:8>)
DMA Destination High Byte (EDMADST<12:8>)
Preliminary
CSUMEN
LINKIE
LINKIF
Bit 4
Pointers will not be modified and no memory will be
written to. The EDMACSH and EDMACSL registers will
contain the calculated checksum. The host controller
may write this value into a packet, compare this value
with a received checksum, or use it for other purposes.
Various protocols, such as TCP and IP, have a checksum
field inside a range of data which the checksum covers.
If such a packet is received and the host controller needs
to validate the checksum, it can do the following:
1.
2.
3.
4.
Writing to the receive buffer is permitted when the write
address is protected by means of the ERXRDPT
Pointers. See Section 7.2 “Receiving Packets” for
additional information.
The IP checksum has unique mathematical properties
which may be used in some cases to reduce the
processing requirements further. Writing to the receive
buffer may be unnecessary in some applications.
When operating the DMA in Checksum mode, it will
take one main clock cycle for every byte included in the
checksum. As a result, if a checksum over 1446 bytes
were performed, the DMA module would require
slightly more than 57.84 s to complete the operation.
TXRTS
Bit 3
TXIE
TXIF
Read the checksum from the packet and save it
to a temporary location
Write zeros to the checksum field.
Calculate a new checksum using the DMA
controller.
Compare the results with the saved checksum
from step 1.
RXEN
Bit 2
r
r
TXERIE
TXERIF
BSEL1
Bit 1
© 2006 Microchip Technology Inc.
RXERIE
RXERIF
BSEL0
Bit 0
on page
Values
Reset
13
13
13
13
13
13
13
13
13
13
13
13
13