ENC28J60-I/SO Microchip Technology, ENC28J60-I/SO Datasheet - Page 3

IC ETHERNET CTRLR W/SPI 28SOIC

ENC28J60-I/SO

Manufacturer Part Number
ENC28J60-I/SO
Description
IC ETHERNET CTRLR W/SPI 28SOIC
Manufacturer
Microchip Technology
Datasheets

Specifications of ENC28J60-I/SO

Package / Case
28-SOIC (7.5mm Width)
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.1 V to 3.6 V
Supply Current (max)
180 mA
Data Rate
10Mbps
No. Of Ports
1
Ethernet Type
IEEE 802.3
Interface Type
SPI
Supply Current
180mA
Supply Voltage Range
3.1V To 3.6V
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Ethernet Connection Type
10Base-T
Digital Ic Case Style
SOIC
No. Of Pins
28
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM163024 - BOARD DEMO PICDEM.NET 2AC164123 - BOARD DAUGHTER ETH PICTAIL PLUSAC164121 - BOARD DAUGHTER PICTAIL ETHERNET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Ethernet Controller Features
• IEEE 802.3 compatible Ethernet controller
• Integrated MAC and 10BASE-T PHY
• Supports one 10BASE-T port with automatic
• Supports Full and Half-Duplex modes
• Programmable automatic retransmit on collision
• Programmable padding and CRC generation
• Programmable automatic rejection of erroneous
• SPI Interface with clock speeds up to 20 MHz
Buffer
• 8-Kbyte transmit/receive packet dual port SRAM
• Configurable transmit/receive buffer size
• Hardware-managed circular receive FIFO
• Byte-wide random and sequential access with
• Internal DMA for fast data movement
• Hardware assisted checksum calculation for vari-
Medium Access Controller (MAC)
Features
• Supports Unicast, Multicast and Broadcast
• Programmable receive packet filtering and
Physical Layer (PHY) Features
• Loopback mode
• Two programmable LED outputs for LINK, TX,
© 2006 Microchip Technology Inc.
polarity detection and correction
packets
auto-increment
ous network protocols
packets
wake-up host on logical AND or OR of the
following:
- Unicast destination address
- Multicast address
- Broadcast address
- Magic Packet™
- Group destination addresses as defined by
- Programmable pattern matching of up to
RX, collision and full/half-duplex status
64-bit hash table
64 bytes at user-defined offset
Stand-Alone Ethernet Controller with SPI Interface
Preliminary
Operational
• Six interrupt sources and one interrupt output pin
• 25 MHz clock input requirement
• Clock out pin with programmable prescaler
• Operating voltage of 3.1V to 3.6V (3.3V typical)
• 5V tolerant inputs
• Temperature range: -40°C to +85°C Industrial,
• 28-pin SPDIP, SSOP, SOIC, QFN packages
Package Types
RESET
* Reserved pin; always leave disconnected.
0°C to +70°C Commercial (SSOP only)
V
28-Pin SPDIP, SSOP, SOIC
28-pin QFN
SSRX
SCK
NC*
SO
CS
SI
CLKOUT
RESET
RBIAS
V
TPIN+
TPIN-
V
SSRX
ENC28J60
SCK
NC*
V
CAP
INT
SO
CS
SS
SI
1
2
3
4
5
6
7
28 27 26 25 24 23 22
8 9 10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ENC28J60
11 12 13 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
21
20
19
18
17
16
15
DS39662B-page 1
V
LEDA
LEDB
V
OSC2
OSC1
V
V
V
V
V
TPOUT+
TPOUT-
V
DD
DDOSC
SSOSC
SSPLL
DDPLL
DDRX
SSTX
DDTX
V
OSC2
OSC1
V
V
V
V
DDOSC
SSOSC
SSPLL
DDPLL
DDRX

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