AD1981BJSTZ Analog Devices Inc, AD1981BJSTZ Datasheet - Page 30

• Manufacturer Part Number: AD1981BJSTZ
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981BJSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 3 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3/4.5V
• Single Supply Voltage (max): 3.47/5.5V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1981B
Bit
VREFD
VREFH
MADST
2CMIC
MADPD
FMXE
DAM
LODIS
MSPLT
DACZ
Mnemonic
V
V
Mixer ADC Status Bit
2-Channel MIC Select
Mixer ADC Power-Down
Front DAC into Mixer
Enable
Digital Audio Mode
LINE_OUT Disable
Mute Split
DAC Zero-Fill
REFOUT
REFOUT
Disable
High
Function
This bit disables V
0 = V
1 = V
This bit changes V
0 = V
1 = V
This bit indicates status of the mixer digitizing ADC (left and right channels).
0 = Mixer ADC not ready.
1 = Mixer ADC ready.
This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that use a
stereo microphone array. This register works in conjunction with the MS bit in Register 0x20.
0 = MIC1 or MIC2 (determined by the MS bit) is routed to the record selector’s left and right MIC
channels, as well as to the mixer (reset default).
1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record
selector’s right MIC channel. In this mode, the MS bit should be set low, and MIC1 can still be
enabled into the mixer.
This bit controls power-down for mixer digitizing ADC.
0 = Mixer ADC is powered on (default).
1 = Mixer ADC is powered down.
This bit controls the front (main) DAC to mixer mute switches.
0 = Front DAC outputs are allowed to sum into the mixer (reset default).
1 = Front DAC outputs are muted into the mixer (blocked).
PCM DAC outputs bypass the analog mixer and are sent directly to the codec output.
This bit disables the LINE_OUT pins (L/R), placing them into high Z mode so that the assigned
output audio jack can be shared for the input function (or other function).
0 = LINE_OUT pins have normal audio drive capability (reset default).
1 = LINE_OUT pins are placed into high Z mode.
This bit allows separate mute control bits for the master, headphone, LINE_IN, CD, AUX, and PCM
volume control registers as well as for the record gain register.
0 = Both left- and right-channel mutes are controlled by Bit 15 in the respective registers (reset
default).
1 = Bit 15 affects only the left-channel mute, and Bit 7 affects only the right-channel mute.
This bit determines DAC data fill under starved conditions.
0 = DAC data is repeated when DACs are starved for data (reset default).
1 = DAC is zero-filled when DACs are starved for data.
REFOUT
REFOUT
REFOUT
REFOUT
pin is driven by the internal reference (reset default).
pin is placed into high Z out mode.
pin is set to 2.25 V output (reset default).
pin is set to 3.70 V output.
REFOUT
REFOUT
Rev. C | Page 30 of 32
, placing it into high Z out mode. This bit overrides the VREFH bit selection.
from 2.25 V to 3.70 V for MIC bias applications.